A single electron transistor (SET) has characteristics for repeating increase and decrease of a current flowing between a drain and a source according to a bias voltage applied to a gate electrode. Researches on an application circuit applying electrical characteristics of the SET in addition to the SET have been actively carried out (see: “Correlated discrete transfer of single electrons in ultrasmall tunnel junctions” by K.K. Likharev, IBM J. Res. Develop, vol. 32, pp. 144-158, January 1988, and “Complementary digital logic based on the Coulomb blockade” by J. R. Tucker, J. Appl. Phys., vol. 72, pp. 4399-4413, November, 1992).
FIG. 1 is a circuit diagram of a universal literal gate (ULG) using a single gate SET and a metal-oxide-semiconductor (MOS) transistor. The ULG 100 includes a current source CS, a first MOS transistor M1, and the SET.
The current source CS supplies a predetermined current Io to the first MOS transistor M1 and the SET. The first MOS transistor M1 transmits the current Io supplied from the current source CS connected to a terminal to the SET connected to the other terminal in response to a bias voltage Vgg applied to a gate. The SET changes a value and a phase of a current Id supplied from a terminal according to an input voltage Vin applied to a gate.
FIG. 2 is view illustrating a relationship between the input voltage Vin of the ULG illustrated in FIG. 1 and a current Id flowing to the SET, and FIG. 3 is a view illustrating a relationship between the input voltage Vin of the ULG illustrated in FIG. 1 and an output voltage Vout.
Referring to FIGS. 2 and 3, as the input voltage Vin increases, increase and decrease of the current Id flowing through the ULG 100 are repeated, and the voltage Vout of the output terminal is changed according to a period that is the same as the repeat period. Here, the current Io that is supplied from the current source CS is constant.
Referring to FIGS. 1, 2, and 3, when a fixed bias voltage Vgg is applied to a gate terminal of the first MOS transistor M1, a drain voltage Vds of the SET is maintained at a constant voltage (Vgg−Vth). Here, the drain voltage (VggVth) of the SET is a voltage low enough to satisfy the coulomb-blockade condition of the SET, and therefore, the drain current of the SET is periodically increased and decreased according to the input voltage Vin.
Specifically, there is a section A in which the current Id flowing through the ULG 100 is larger than the fixed current Io supplied from the current source CS according to the input voltage Vin. In this case, a voltage level of the output terminal Vout has to be lowered so that a current corresponding to a difference (Id−Io) between the two currents is supplied to the ULG 100 through the first MOS transistor M1. In addition, there is a section B in which the current flowing through the ULG 100 is smaller than the fixed current Io supplied from the current source CS according to the input voltage Vin. In this case, the voltage level of the output terminal Vout has to be increased so that the current corresponding to the difference (Io−Id) between the two currents is blocked by the first MOS transistor M1. Consequently, as illustrated in FIG. 3, characteristics such as a square waveform having a voltage swing can be represented.
FIG. 4 is a circuit diagram of a quantizer using the ULG illustrated in FIG. 1. Referring to FIG. 4, the quantizer further includes a second MOS transistor M2 in addition to the ULG 100 illustrated in FIG. 1. The input signal Vin is simultaneously applied to a gate terminal Cg of the SET and the output terminal Vout through the second MOS transistor M2 in response to a control clock signal CLK.
FIG. 5 is a view illustrating a relationship between the input voltage Vin of the quantizer illustrated in FIG. 4 and the current Id flowing to the SET. FIG. 6 is a view illustrating a relationship between the input voltage Vin of the quantizer illustrated in FIG. 4 and the voltage level of the output node Vout.
Since FIG. 5 is the same as FIG. 2 described above, so that a description is omitted. Referring to FIG. 6, as the input voltage Vin increases, the voltage level Vout of the output node has a shape of stairs, so that the quantizer illustrated in FIG. 4 is a multi-valued quantizer representing a plurality of values instead of representing only two values including logic high and logic low values illustrated in FIG. 3.
The multi-valued quantizer may be implemented by using the second MOS transistor M2 and the control clock signal CLK illustrated in FIG. 4, and a voltage level represented as a stair and an adjacent stair representing a different voltage level can be distinguished by each period of the control clock signal CLK. The input voltage Vin is transmitted to the output node Vout in addition to the gate terminal Cg of the SET through the second MOS transistor M2 by the control clock signal CLK. In this case, the voltage level Vout of the output terminal of the quantizer responses on the basis of the received input voltage Vin. Therefore, since the voltage level Vout of the output node is influenced by the input signal Vin that is newly transmitted by a next control clock signal CLK, when the input voltage Vin is received again by the control clock signal CLK, the voltage level Vout of the output node is changed according to the received input voltage Vin. When the input voltage Vin is continuously applied, correspondingly, a plurality of voltage levels Vout of the output node can be obtained.
FIG. 7 is a view illustrating a multi-valued static random access memory (SRAM) using the quantizer illustrated in FIG. 4. Referring to FIG. 7, the multi-valued SRAM includes five MOS transistors M1 to M5 and an SET.
The third MOS transistor M3 has a terminal connected to a bit line BL and a gate connected to a word line WL. The second MOS transistor M2 has a terminal connected to a first voltage source terminal Vdd and the other terminal and a gate connected to a charge storage node SN. The first MOS transistor M1 has a terminal connected to the charge storage node SN and a gate connected to a second voltage source terminal Vss.
The SET has a terminal connected to the other terminal of the first MOS transistor M1, the other terminal connected to the second voltage source terminal Vss, and a gate connected to the charge storage node SN. The fourth MOS transistor M4 has a terminal connected to the second voltage source terminal Vss and a gate connected to the charge storage node SN. The fifth MOS transistor M5 has a terminal connected to a source line SL, the other terminal connected to the other terminal of the fourth MOS transistor M4, and a gate connected to a sub word line SWL.
FIG. 8 is a waveform diagram of signals used to write (referred to as store) or read data to or from the multi-valued SRAM illustrated in FIG. 7. Referring to FIG. 8, in order to write data to the multi-valued SRAM, a voltage to be written to the multi-valued SRAM has to be precharged to the bit line BL. The voltage to be written is determined by the number of bits to be represented by the multi-valued SRAM, and when it is assumed that two bits are used, four different voltage levels can be obtained. Specifically, the two bits can represent ‘00’, ‘01’, ‘10’, and ‘11’. Here, it is assumed that the voltage level corresponding to ‘00’ is the smallest, and the voltage level corresponding to ‘11’ is the largest.
When the word line WL is enabled in a logic high state after the voltage to be written is precharged to the bit line BL, the third MOS transistor M3 is turned on so as to enable the precharge voltage to be transmitted to the charge storage node SN. Since the transmitted voltage is applied to a gate, a constant current flows to the SET according to the transmitted voltage. Unless power supply is intentionally blocked, the constant current flows from the first voltage source terminal Vdd through the second and first MOS transistors M2 and M1 and the SET to the second voltage source terminal Vss, so that charges stored in the charge storage node SN are not vanished. Therefore, the SRAM illustrated in FIG. 7 does not need a refresh operation and can vary written voltage values, so that the SRAM is specifically the multi-valued SRAM.
In order to read data written to the multi-valued SRAM, the sub word line SWL is enabled, and the data written to the charge storage node SN of the multi-valued SRAM can be detected through the source line SL precharged at a predetermined voltage. Specifically, since the charge storage node SN is applied to the gate of the fourth MOS transistor M4, a current that can flow through the fourth MOS transistor M4 is determined by the charge storage node SN. In this case, a current flowing to the source line SL precharged at the predetermined voltage can also be changed by the charge storage node SN, so that the current is also detected to read the data value written to the multi-valued SRAM.
However, the conventional multi-valued SET SRAM continuously flows a current of about Id to the SET per cell in order to maintain the data, so that there is a problem in that a standby current is significantly increased as a density is increased.
In addition, in order to configure an array using the conventional multi-valued SET SRAM cells, two row lines WL and SWL and two column lines BL and SL are required per cell, so that there is a problem in that the entire area of the memory is increased.